Research Article

From fault tolerance to fault detection: A DHR-based contrastive testing method and its validation on ADAS

Purple Mountain Laboratories, Nanjing 211111, China

^* Corresponding author (email: This email address is being protected from spambots. You need JavaScript enabled to view it. )
^** Corresponding author (email: This email address is being protected from spambots. You need JavaScript enabled to view it. )

Received: 24 October 2025
Revised: 23 January 2026
Accepted: 4 February 2026

Abstract

Many modern complex systems, such as advanced driver assistance systems (ADAS), face the problems of dynamic and diverse test environments and unpredictable test results when performing black-box testing. This may lead to imprecise fault localization and low test efficiency. Inspired by the Dynamic Heterogeneous Redundancy (DHR) architecture in the field of network security, this paper proposes a contrastive testing method to solve these problems. The core innovation of this method is the concept transfer from “fault tolerance redundancy” to “error detection redundancy”. This approach uses a set of functionally equivalent but heterogeneous executors to expose defects in the Unit under Test (UUT) through output inconsistencies. The proposed framework is built on a hierarchical system architecture, which supports progressive testing from the top module to the bottom module to complete the precise localization of defects. The heterogeneity of these reference implementations (RIs) is the key to reducing common mode failures, which is ensured by a multidimensional quantization model. The majority consensus adjudication automates defect detection by treating the output of the majority of RIs as a behavioral baseline, eliminating the need for a priori expectations. Experimental results on an ADAS show that our approach reduces the testing time by 63.9% and successfully transitions the DHR architecture from cybersecurity to the testing domain, providing a robust and scalable solution for testing heterogeneous and uncertain systems under intellectual property (IP) constraints.